The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method and structures for manufacturing bonding pad structures for advanced integrated circuit devices. But it would be recognized that the invention has a much broader range of applicability.
Integrated circuits have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Conventional integrated circuits provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of integrated circuits.
Increasing circuit density has not only improved the complexity and performance of integrated circuits but has also provided lower cost parts to the consumer. An integrated circuit or chip fabrication facility can cost hundreds of millions, or even billions, of U.S. dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of integrated circuits on it. Therefore, by making the individual devices of an integrated circuit smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in integrated fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. Additionally, as devices require faster and faster designs, process limitations exist with certain conventional processes and materials.
An example of such a process is the manufacture of bonding pad structures of integrated circuit devices. Such bonding pad structure has traditionally became smaller and smaller and occupy a smaller region of silicon real estate. Although there have been significant improvements, such bond pad designs still have many limitations. As merely an example, these designs must become smaller and smaller but still provide sufficient mechanical properties to support the bonded wire structure. The pad designs often peel and lead to other quality and reliability problems. Additionally, the conventional bonding pad designs using device under pad often require an additional buffer layer that requires complex manufacturing processes and structures. These and other limitations will be described in further detail throughout the present specification and more particularly below.
From the above, it is seen that an improved technique for processing semiconductor devices is desired.